1. Technical Field
The present invention generally relates to a semiconductor device and a method of manufacturing the same, and, more particularly, to a semiconductor device structure adapted for high integration and a manufacturing method thereof.
2. Description of the Related Art
FIG. 1 is a schematic view of the structure of a conventional MOSFET (metal oxide semiconductor field effect transistor) 7 formed on a silicon substrate 1. MOSFET 7 includes a source/drain region 4 and a drain/source region 5 formed in substrate 1 with a channel region 6 therebetween. A gate electrode 3 is insulatively spaced from channel region 6 by a gate insulating film 2. As semiconductor devices have become more highly integrated, the dimensions of device portions such as MOSFETs have been scaled-down. In the case of MOSFETs, such scaling-down can be achieved by reducing the width of the gate electrode, i.e., by reducing the channel length "L". However, it is well-known that if the channel length L is reduced to less than approximately 50 nanometers (nm), so-called short-channel effects become significant, thereby making it difficult to control the threshold voltage of the MOSFET. This can be seen with reference to the graph of FIG. 2 which illustrates the relationship between channel length and threshold voltage. As can be seen in FIG. 2, when the channel length becomes less than about 50 nanometers, the threshold voltage varies as a function of the channel length.
One technique for suppressing short-channel effects is to increase the impurity concentration of channel region 6. As can be seen with reference to FIG. 3 which illustrates the relationship between channel length and channel-impurity concentration for suppressing short-channel effect, when the channel length is reduced to less than 50 nanometers (nm), the channel impurity concentration must be increased to approximately 1.times.10.sup.19 cm.sup.-3 or higher. However, if the channel impurity concentration is increased higher than approximately 7.times.10.sup.18 cm.sup.-3, the tunneling current (leak current) between the PN junctions can affect transistor operation. As a result, a deterioration in drain-to-substrate withstand voltage can occur, possibly disabling the transistor.
In short, although conventional MOSFETs can be scaled down by reducing the channel length, short-channel effects arise if the channel length becomes too small. While increasing the channel impurity concentration can suppress short-channel effects, the range over which the channel-impurity concentration can be increased is restricted in view of the deterioration in withstand voltage. Thus, the scaling-down of conventionally-structured MOSFETs is restricted by factors such as short-channel effect and deterioration in withstand voltage.
It would therefore be desirable to provide a semiconductor device structure which overcomes these limitations.